#ChipScope Core Inserter Project File Version 3.0
#Wed Mar 13 11:00:37 IST 2013
Project.device.designInputFile=D\:\\scratch_rahul\\repo\\cypress\\fx2lp_slaveFIFO2b_xilinx\\fpga_loopback_vhdl\\fx2lp_proj\\fx2lp_loopback\\fx2lp_slaveFIFO2b_loopback_fpga_top.ngc
Project.device.designOutputFile=D\:\\scratch_rahul\\repo\\cypress\\fx2lp_slaveFIFO2b_xilinx\\fpga_loopback_vhdl\\fx2lp_proj\\fx2lp_loopback\\fx2lp_slaveFIFO2b_loopback_fpga_top.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=false
Project.device.outputDirectory=D\:\\scratch_rahul\\repo\\cypress\\fx2lp_slaveFIFO2b_xilinx\\fpga_loopback_vhdl\\fx2lp_proj\\fx2lp_loopback\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=5
Project.filter<0>=
Project.filter<1>=sl*
Project.filter<2>=fifo_*
Project.filter<3>=fifo_data*
Project.filter<4>=*clk*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=CLK_OUT_0
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=2048
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=20
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=fifo_data_out<7>
Project.unit<0>.triggerChannel<0><10>=fifo_data_in<5>
Project.unit<0>.triggerChannel<0><11>=fifo_data_in<4>
Project.unit<0>.triggerChannel<0><12>=fifo_data_in<3>
Project.unit<0>.triggerChannel<0><13>=fifo_data_in<2>
Project.unit<0>.triggerChannel<0><14>=fifo_data_in<1>
Project.unit<0>.triggerChannel<0><15>=fifo_data_in<0>
Project.unit<0>.triggerChannel<0><16>=fifo_pop
Project.unit<0>.triggerChannel<0><17>=fifo_push
Project.unit<0>.triggerChannel<0><18>=slwr_d_n
Project.unit<0>.triggerChannel<0><19>=
Project.unit<0>.triggerChannel<0><1>=fifo_data_out<6>
Project.unit<0>.triggerChannel<0><2>=fifo_data_out<5>
Project.unit<0>.triggerChannel<0><3>=fifo_data_out<4>
Project.unit<0>.triggerChannel<0><4>=fifo_data_out<3>
Project.unit<0>.triggerChannel<0><5>=fifo_data_out<2>
Project.unit<0>.triggerChannel<0><6>=fifo_data_out<1>
Project.unit<0>.triggerChannel<0><7>=fifo_data_out<0>
Project.unit<0>.triggerChannel<0><8>=fifo_data_in<7>
Project.unit<0>.triggerChannel<0><9>=fifo_data_in<6>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=19
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
